一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现

张茜; 詹明; 章坚武; 王富龙; 冯云开; 唐浩

doi:10.11959/j.issn.1000-0801.2022023

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一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现

研究与开发 | 更新时间：2024-06-05

- 一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现
- Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations
- 电信科学 2022年38卷第2期页码：47-58
- 作者机构：
  
  1. 西南大学，重庆 400715
  2. 杭州电子科技大学，浙江杭州 310018
- 作者简介：
  
  [ "张茜（1996- ），女，西南大学硕士生，主要研究方向为信号与信息处理" ]
  [ "詹明（1975- ），男，博士，西南大学学院教授、博士生导师，中国电子学会会员，主要研究方向为信道编码理论与技术、无线传感器网络、超高性能工业无线控制" ]
  [ "章坚武（1961- ），男，博士，杭州电子科技大学教授、博士生导师，中国电子学会高级会员，浙江省通信学会常务理事，主要研究方向为移动通信、多媒体信号处理与人工智能、通信网络与信息安全" ]
  [ "王富龙（1995- ），男，西南大学硕士生，主要研究方向为信号与信息处理" ]
  [ "冯云开（1995- ），男，西南大学硕士生，主要研究方向为信号与信息处理" ]
  [ "唐浩（1996- ），男，西南大学硕士生，主要研究方向为信号与信息处理" ]
- 基金信息：
  
  国家自然科学基金资助项目;The National Natural Science Foundation of China(61671390)
- DOI：10.11959/j.issn.1000-0801.2022023
  中图分类号： TN929
- 网络出版日期：2022-02，
  
  纸质出版日期：2022-02-20
- 稿件说明：
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张茜, 詹明, 章坚武, 等. 一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现[J]. 电信科学, 2022,38(2):47-58.

Qian ZHANG, Ming ZHAN, Jianwu ZHANG, et al. Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations[J]. Telecommunications science, 2022, 38(2): 47-58.
张茜, 詹明, 章坚武, 等. 一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现[J]. 电信科学, 2022,38(2):47-58. DOI： 10.11959/j.issn.1000-0801.2022023.

Qian ZHANG, Ming ZHAN, Jianwu ZHANG, et al. Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations[J]. Telecommunications science, 2022, 38(2): 47-58. DOI： 10.11959/j.issn.1000-0801.2022023.

摘要

为满足无线通信中高吞吐、低功耗的要求，并行译码器的结构设计得到了广泛的关注。基于并行Turbo码译码算法，研究了前后向度量计算中的对称性，提出了一种基于前后向合并计算的高效并行 Turbo 码译码器结构设计方案，并进行现场可编程门阵列（field-programmable gate array，FPGA）实现。结果表明，与已有的并行 Turbo 码译码器结构相比，本文提出的设计结构使状态度量计算模块的逻辑资源降低 50%左右，动态功耗在125 MHz频率下降低5.26%，同时译码性能与并行算法的译码性能接近。

Abstract

In order to achieve the requirement of high throughput and low-power in wireless communication

a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics

a low-resource parallel Turbo decoder architecture scheme based on merging the forward and backward state metrics calculation modules was proposed

and effectiveness of the new architecture was demonstrated through field-programmable gate array (FPGA) hardware realization.The results show that

compared with the existing parallel Turbo decoder architectures

the proposed design architecture reduces the logic resource of state metrics calculation module about 50%

while the dynamic power dissipation of the decoder architecture is decreased by 5.26% at the frequency of 125 MHz.Meanwhile the decoding algorithm is close to the decoding performance of the parallel algorithm.

关键词

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references

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