基于频偏矫正辅助的Starlink下行信号帧同步轻量化电路设计

韩煜; 周雪齐; 沈雷

doi:10.11959/j.issn.1000-0801.2026004

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基于频偏矫正辅助的Starlink下行信号帧同步轻量化电路设计

研究与开发 | 更新时间：2026-03-05

- 基于频偏矫正辅助的Starlink下行信号帧同步轻量化电路设计
- Design of Starlink downlink signal frame synchronization lightweight circuit based on frequency offset correction assistance
- 电信科学 2026年42卷第2期页码：161-172
- 作者机构：
  
  1.中国电子科技集团公司第36研究所电磁空间安全全国重点实验室，浙江嘉兴314033
  2.杭州电子科技大学通信工程学院，浙江杭州 310018
- 作者简介：
  
  [ "韩煜（1978- ），男，中国电子科技集团公司第36研究所电磁空间安全全国重点实验室副研究员，主要研究方向为自适应信号处理、通信与语音信号处理。" ]
  [ "周雪齐（1999- ），男，杭州电子科技大学硕士生，主要研究方向为数字信号处理。" ]
  [ "沈雷（1979- ），男，博士，杭州电子科技大学通信工程学院教授、博士生导师，主要研究方向为数字图像处理、模式识别。" ]
- 基金信息：
- DOI：10.11959/j.issn.1000-0801.2026004
  中图分类号： TN911.72
- 收稿：2025-04-30，
  
  修回：2025-04-18，
  
  录用：2025-04-30，
  
  纸质出版：2026-02-20
- 稿件说明：
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韩煜,周雪齐,沈雷.基于频偏矫正辅助的Starlink下行信号帧同步轻量化电路设计[J].电信科学,2026,42(02):161-172.

Han Yu,Zhou Xueqi,Shen Lei.Design of Starlink downlink signal frame synchronization lightweight circuit based on frequency offset correction assistance[J].Telecommunications Science,2026,42(02):161-172.
韩煜,周雪齐,沈雷.基于频偏矫正辅助的Starlink下行信号帧同步轻量化电路设计[J].电信科学,2026,42(02):161-172. DOI： 10.11959/j.issn.1000-0801.2026004.

Han Yu,Zhou Xueqi,Shen Lei.Design of Starlink downlink signal frame synchronization lightweight circuit based on frequency offset correction assistance[J].Telecommunications Science,2026,42(02):161-172. DOI： 10.11959/j.issn.1000-0801.2026004.

摘要

传统正交频分复用（orthogonal frequency division multiplexing，OFDM）帧同步方法，如基于前导序列、基于导频、基于深度学习的帧同步算法在面对Starlink高速率、高动态通信环境时局限于单路计算思路，且具有较多的资源消耗和较高的时钟需求。而基于差分相移键控（symmetric differential phase shift keying，SDPSK）调制的多路并行帧同步算法虽然引入频偏矫正和本地前导序列相关使得性能上有所提升并降低了时钟需求，但加大了计算量和硬件资源占用。针对以上情况，基于Starlink公开前导结构，提出了四路并行的基于频偏矫正辅助的Starlink下行信号帧同步轻量化电路设计。首先，设计基于延时相关复用的轻量化粗帧同步和频偏估计结构使电路在频偏估计时不需要再次计算延时相关值。然后，提出基于四路并行直接数字式频率合成器（direct digital synthesizer，DDS）的轻量化频偏矫正模块避免单路信号在多路结构下变频时需要缓存。最后，设计基于符号相关和查找表复数乘法器的轻量化精帧同步结构减少了本地序列和信号相关的资源耗用，在保证性能的前提下使得查找表（look-up table，LUT）、查找表随机存取存储器（look-up table random access memory，LUTRAM）、触发器（flip-flop，FF）、块随机存取存储器（block random access memory，BRAM）资源分别节省了7%、2%、5%和8%。对电路编写verilog代码进行现场可编程门阵列（field programmable gate array，FPGA）实现，并通过Xilinx生产的xczu47dr芯片上板验证了其资源占用及性能表现。

Abstract

Traditional OFDM frame synchronization methods

such as preamble-sequence-based

pilot-based

and deep learning-based frame synchronization algorithms

are limited to single-channel computing ideas

resource consumption

and high clock requirements in the face of Starlink’s high-speed and high-dynamic communication environment.However

although the multi-channel parallel frame synchronization algorithm based on SDPSK modulation introduces frequency offset correction and local preamble sequence correlation to improve the performance and reduce the clock requirements

it increases the amount of computation and hardware resources. In view of the above situation

a four-way parallel design of Starlink downlink signal frame synchronization lightweight circuit based on frequency offset correction assistance was proposed. Firstly

a lightweight coarse frame synchronization and frequency offset estimation structure based on delay correlation multiplexing was designed

so that the circuit would not need to calculate the delay correlation value again during frequency offset estimation. Then

a lightweight frequency offset correction module based on four-channel parallel DDS was proposed to avoid the resource consumption of buffering when a single-channel signal was converted under the multi-channel structure. Finally

the lightweight fine frame synchronization structure based on symbolic correlation and look-up table complex multiplier was designed to reduce the resource consumption of local sequence and signal

and the resources of LUT

LUTRAM

FF and BRAM were saved by 7%

5% and 8% respectively under the premise of ensuring performance. Based on the Starlink open leading structure

a lightweight circuit design of Starlink downlink signal frame synchronization based on frequency offset correction assistance was proposed

and verilog code was written for FPGA implementation

and its resource occupation and performance were verified by the xczu47dr chip-on-board produced by Xilinx.

关键词

Keywords

references

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