Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations

Qian ZHANG; Ming ZHAN; Jianwu ZHANG; Fulong WANG; Yunkai1 FENG; Hao TANG

doi:10.11959/j.issn.1000-0801.2022023

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Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations

Research and Development | 更新时间：2024-06-05

- Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations
- Telecommunications Science Vol. 38, Issue 2, Pages: 47-58(2022)
- 作者机构：
  
  1. 西南大学，重庆 400715
  2. 杭州电子科技大学，浙江杭州 310018
- 作者简介：
- 基金信息：
- DOI：10.11959/j.issn.1000-0801.2022023
  CLC： TN929
- Published Online：2022-02，
  
  Published：20 February 2022
- 稿件说明：
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Qian ZHANG, Ming ZHAN, Jianwu ZHANG, et al. Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations[J]. Telecommunications science, 2022, 38(2): 47-58.
DOI：

Qian ZHANG, Ming ZHAN, Jianwu ZHANG, et al. Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations[J]. Telecommunications science, 2022, 38(2): 47-58. DOI： 10.11959/j.issn.1000-0801.2022023.

摘要

为满足无线通信中高吞吐、低功耗的要求，并行译码器的结构设计得到了广泛的关注。基于并行Turbo码译码算法，研究了前后向度量计算中的对称性，提出了一种基于前后向合并计算的高效并行 Turbo 码译码器结构设计方案，并进行现场可编程门阵列（field-programmable gate array，FPGA）实现。结果表明，与已有的并行 Turbo 码译码器结构相比，本文提出的设计结构使状态度量计算模块的逻辑资源降低 50%左右，动态功耗在125 MHz频率下降低5.26%，同时译码性能与并行算法的译码性能接近。

Abstract

In order to achieve the requirement of high throughput and low-power in wireless communication

a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics

a low-resource parallel Turbo decoder architecture scheme based on merging the forward and backward state metrics calculation modules was proposed

and effectiveness of the new architecture was demonstrated through field-programmable gate array (FPGA) hardware realization.The results show that

compared with the existing parallel Turbo decoder architectures

the proposed design architecture reduces the logic resource of state metrics calculation module about 50%

while the dynamic power dissipation of the decoder architecture is decreased by 5.26% at the frequency of 125 MHz.Meanwhile the decoding algorithm is close to the decoding performance of the parallel algorithm.

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references

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