Design on the full-dimensional reconfiguration polymorphic network switching chip architecture

Yu LI; Zhaozhao LI; Ping LYU; Qinrang LIU

doi:10.11959/j.issn.1000-0801.2023129

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Design on the full-dimensional reconfiguration polymorphic network switching chip architecture

Topic: Polymorphic Network | 更新时间：2024-06-05

- Design on the full-dimensional reconfiguration polymorphic network switching chip architecture
- Telecommunications Science Vol. 39, Issue 6, Pages: 22-32(2023)
- 作者机构：
  
  1. 清华大学集成电路学院，北京 100084
  2. 网络通信与安全紫金山实验室，江苏南京 211111
  3. 中国人民解放军战略支援部队信息工程大学信息技术研究所，河南郑州 450002
- 作者简介：
- 基金信息：
- DOI：10.11959/j.issn.1000-0801.2023129
  CLC： TP393
- Published Online：2023-06，
  
  Published：20 June 2023
- 稿件说明：
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Yu LI, Zhaozhao LI, Ping LYU, et al. Design on the full-dimensional reconfiguration polymorphic network switching chip architecture[J]. Telecommunications science, 2023, 39(6): 22-32.
DOI：

Yu LI, Zhaozhao LI, Ping LYU, et al. Design on the full-dimensional reconfiguration polymorphic network switching chip architecture[J]. Telecommunications science, 2023, 39(6): 22-32. DOI： 10.11959/j.issn.1000-0801.2023129.

摘要

当前，IP 网络结构僵化、可扩展性差、安全性差。为了解决这些问题，学者们提出了多模态网络的概念，并成为当前的研究热点。可编程网络交换芯片是多模态网络的实现基础。提出了一种全维可重构的多模态网络交换芯片架构，以嵌入式 FPGA 为基础实现了多模态网络的端口级、比特级细粒度可重构，以自主设计的网络处理单元为基础实现了网络交换引擎的粗粒度可重构，使网络交换芯片具备了全维可重构的能力，为多模态网络的数据层提供了实现基础。还提出了一种改进的位矢量查找算法，能够以较小的资源占用实现较快的流表查找，提升网络交换性能，展现出较高的实用性。

Abstract

At present

IP network has the problems of rigid structure

poor scalability and poor security.To solve these problems

the concept of polymorphic network has been proposed by researchers and gradually become a research hotspot.The programmable network switching chip is the basis of polymorphic network implementation.Therefore

a full-dimensional reconfigurable polymorphic network switching chip architecture was proposed.Based on eFPGA in the chip

the port-level and bit-level fine-grained reconfigurable polymorphic network was realized.Based on self-designed process element (PE)

the coarse-grained reconfigurable network switching engine was realized.Thereby the full-dimensional reconfigurable polymorphic network switching chip was realized and laid the foundation for the data layer of polymorphic network.To improve the network switching performance

an improved bit vector algorithm was proposed

which could realize fast flow table lookup with a smaller resource consumption.The proposed algorithm has showed its practicability in the research.

关键词

Keywords

references

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